CS537 9/30
Brief Page Table  Per Process large => in memory Upon every memory reference: address translation What does the hardware need to know? location of page table (Page Table Base Register[PTBR] in MMU) Points to start of page table of currently running process Privileged Paging: Too Slow To do translation: Fetch Page Table Entry Extra memory reference Solution: Hardware (Translation Lookaside Buffer [TLB]) in CPU hardware that holds some number of “popular” translation Method: When Virtual address -> TLB, If VPN is in the TLB, “hit” use PFN in TLB, form physical addr, perform mem access If not, “miss”....