CS537 9/30

Brief

Page Table


• Per Process
• large => in memory
• Upon every memory reference: address translation
• What does the hardware need to know?
  • location of page table (Page Table Base Register[PTBR] in MMU)
    • Points to start of page table of currently running process
    • Privileged

Paging: Too Slow

• To do translation: Fetch Page Table Entry
  • Extra memory reference

Solution: Hardware (Translation Lookaside Buffer [TLB])

• in CPU hardware that holds some number of “popular” translation
• Method: When Virtual address -> TLB,
  1. If VPN is in the TLB, “hit” use PFN in TLB, form physical addr, perform mem access
  2. If not, “miss”. Hardware: use PTBR to access page table, update TLB with necessary info. Try again => TLB hit
  • What happens if TLB is full?
    • Replacement

Page Table Structure

• Linear Page Table: Array
  • Valid: v=1 prog can legally access the page, v=0 not
  • PFN: if v=1, physical frame that holds the page
  • Protection: read only, read/write, execute

TLB Contents

• Similar but different
  • VPN in table (Hardware is going to search in parallel to see if there is a hit)
  • PFN
  • Protection Bit
  • Valid Bit in TLB means that this entry has valid translation
    • e.g. $P_1$ running, TLB fills with $P_1$ VPN => PFN translation
    • timer interrupt, scheduler => $P_2$
    • Can we run $P_2$ => no (because valid translations for $P_1$ in TLB)
    • Flush TLB (set valid for all entries to 0)
    • PID

H/W Managed TLB:

• TLB miss => hardware accesses page table + update TLB